1. Field of the Invention
This invention relates in general to a memory and specifically to a memory with charge storage locations.
2. Description of the Related Art
When operating a memory device, a voltage is applied to a selected word line coupled to the gate electrode, while all other word lines are either grounded or floating. As memory devices within an array are formed closer together to decrease die size, the word line that is adjacent the selected word line may undesirably become capacitively coupled to the selected word line. Although an insulating material lies between the two word lines, the distance between them may be small enough to enable coupling. This undesirable coupling can occur in any memory device, but especially occurs in non-planar transistors, such as FinFETs. If coupling occurs, the adjacent cell may be undesirably programmed, erased, or read. Therefore, a need exists for mitigating such coupling.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted.